module multiplex(muIn1,muIn2,muCin2,muOut,mucout1,mucout2,mucout);
	input [31:0] muIn1;
	input [31:0] muIn2;
	input muCin2;
	output reg [31:0] muOut;
	input mucout1, mucout2; 
	output reg mucout;
	
	always@* begin
		case(muCin2)
			1'b0 : muOut = muIn1;
			1'b0 : mucout = mucout1;
			1'b1 : muOut = muIn2;
			1'b1 : mucout = mucout2;
		endcase
		end
endmodule
		